1. Field of the Invention
The present invention relates to a structure of a MOS transistor, and more particularly to a structure of a MOS transistor exhibiting an enhanced current drive capability while maintaining a high resistance to hot carriers.
2. Description of the Related Art
In recent years, various kinds of problems originating from the generation of hot carriers are being revealed accompanying the advances in fine patterning of the MOS transistor. This is caused by the circumstance that despite the reduction in the gate length of the MOS transistor as a result of fine patterning, its operating voltage is not lowered in proportion to the reduction in the gate length.
As a technique of realizing fine patterning without deteriorating the characteristics of the MOS transistor there has been known the scaling rule. This is a technique by which circuit parameters, such as the power supply voltage, are reduced in proportion to the reduction in the gate length. Thus, according to the scaling rule, when the channel length L is reduced to 1/k of its value, for example, the power supply voltage is also reduced to 1/k of the original value in the same manner as for the channel length. In practice, however, the MOS transistor is operated without reducing the power supply voltage to 1/k as required by the scaling rule. The reasons for the negligence of the rule are due to disadvantages that a satisfactory improvement effect of circuit characteristics cannot be obtained when the MOS transistor is operated at a low power supply voltage according to the scaling rule, and that it requires the supply of such a low power supply voltage from the outside. For these reasons, in the actual integrated circuits, MOS transistors are being used with reduced channel length but without corresponding change in the power supply voltage.
When fine patterning of the MOS transistor is promoted without lowering the power supply voltage, as in the above, the internal electric field of the MOS transistor is increased all the more. The internal electric field of the MOS transistor shows a maximum value in the vicinity of the drain, and impact ionization takes place in that region. Carriers gaining high energy generated by this phenomenon are referred to as hot carriers.
These hot carriers cause a variety of problems which harm the reliability of the MOS transistor. For example, traps and surface levels may be created by the implantation of the hot carriers into the gate oxide film, and the characteristics of the MOS transistor will be changed by the capture of the hot carriers by the traps and surface levels. As a result, a change in the threshold voltage and reduction in the transconductance gm will be brought about. Under these circumstances, various MOS transistor structures have been proposed in order to suppress the generation of the hot carriers which cause these problems. The doubly diffused drain (DDD) structure and the lightly doped drain (LDD) are examples of them. Both of the MOS transistors with DDD structure and LDD structure are structures provided with a lightly doped impurity region in parts close to the channel region of the drain region intended for relaxation of the electric field intensity.
The MOS transistor with DDD structure and the MOS transistor with LDD structure will now be described in the following.
First, the structure and the fabrication method of the MOS transistor with DDD structure will be described. FIG. 10(a) through FIG. 11(b) are sectional views showing the fabrication method of the MOS transistor with DDD structure arranged in the order of processes.
First, as shown in FIG. 10(a), an element isolation insulating film 52 is formed by a selective oxidation method on the surface of a p-type semiconductor substrate 51. Then, a gate oxide film 53 is formed by subjecting the sample to a thermal oxidation.
Next, as shown in FIG. 10(b), a gate electrode 54 is formed on the gate oxide film 53.
Then, as shown in FIG. 10(c), a first n-type impurity, phosphorus 55, is implanted into the p-type semiconductor substrate 51 by ion implantation. By so doing, a first n-type impurity layer 55a is formed in self-alignment with the gate electrode 54. In this case, the ion implantation energy is 20-30 keV, and the dose of the ions is 1xc3x971014 to 5xc3x971014 cmxe2x88x922 
Further, as shown in FIG. 11(a), a second n-type impurity, arsenic 54, is implanted into the p-type semiconductor substrate 51 by ion implantation. By so doing, a second n-type impurity layer 56a is formed in selfalignment with the gate electrode 54. In this case, the ion implantation energy is 30-50 keV, and the dose is 1xc3x971015 to 5xc3x971015 cmxe2x88x922.
Next, after forming a layer insulating film 60 on the entire surface and forming a contact hole, phosphorus 55 and arsenic 56 implanted in the p-type semiconductor substrate are thermally diffused by subjecting the sample to a heat treatment. In this case, since an impurity with a large diffusion coefficient diffuses to a wider area than an impurity with a small diffusion coefficient does, phosphorus having a larger diffusion coefficient compared with arsenic diffuses over a wider area. Because of this, as shown in FIG. 11(b), there is obtained a structure (DDD structure) in which the impurity layer containing phosphorus with larger diffusion coefficient surrounds the periphery of the impurity layer containing arsenic with smaller diffusion coefficient.
Next, the structure and a method of fabrication of a MOS transistor with LDD structure will be described. FIG. 12(a) through FIG. 13(c) are sectional views showing the fabrication method of a MOS transistor with LDD structure arranged in the order of fabrication processes.
As shown in FIG. 12(a), an element isolation film 72 is formed on the surface of a p-type semiconductor substrate by selective oxidation. Then, a gate oxide film 73 is formed by subjecting the sample to a thermal oxidation.
Next, as shown in FIG. 12(b), a gate electrode 74 is formed on the gate oxide film 73.
Then, as shown in FIG. 12(c), a first n-type impurity, phosphorus 75, is implanted into the p-type semiconductor substrate 71 by ion implantation. By so doing, a first n-type impurity layer 75a is formed in self-alignment with the gate electrode 74. In this case, the ion implantation energy is 20-30 keV, and the dose is 5xc3x971012 to 5xc3x971013 cmxe2x88x922.
Then, as shown in FIG. 13(a), a sidewall insulating film 77 is formed on the sidewall of the gate electrode 74. This sidewall insulating film 77 is obtained by forming an insulating film such as silicon oxide film on the principal surface of the semiconductor substrate using CVD or the like, then removing the component corresponding to the thickness of the formed insulating film by an isotropic etching.
Next, as shown in FIG. 13(b), a second n-type impurity, arsenic 76, is implanted into the p-type semiconductor substrate 71. By so doing, a second n-type impurity layer 76a is formed in self-alignment with the gate electrode 74 and the sidewall insulating film 77. In this case, the ion implantation energy is 30-50 keV, and the dose is 1xc3x971015 to 5xc3x971015 cmxe2x88x922.
Next, as shown in FIG. 13(c), after forming a layer insulating film 80 on the entire surface and forming a contact hole or the like, a metallic wiring 84 is formed selectively, completing a MOS transistor with LDD structure. However, the MOS transistor with DDD structure has a problem in that it tends to give rise to the short channel effect. As is well known, the short channel effect is a phenomenon in which a depletion layer extending from the source-drain diffused layer affects the depletion layer extending from the MOS surface to reduce the effective impurity concentration of the substrate. This effect gives rise to various kinds of problems related directly to the abnormality or reduction in the reliability of the circuit operation, such as the lowering of the threshold voltage, the increase in the dependence of the threshold voltage on the drain voltage, or the like. In particular, as the gate length is decreased to less than 1 xe2x96xa1m, the rate of the width of the depletion layer extending from the source-drain diffused layer to the gate length becomes considerably large, and the short channel effect is exhibited more conspicuously.
As the cause of generation of the short channel effect, there may be mentioned the involvement of the thickness W of the MOS surface depletion layer and the P-N junction depletion layer, and the junction depth Xj of the sourcedrain diffused layer. Generally speaking, it is believed that the short channel effect is less likely to occur, and hence is more preferable, when the values of the thickness W of these depletion layers and the junction depth Xj are small. That the short channel effect is liable to occur in the MOS transistor with DDD structure is precisely due to these reasons. Namely, since two kinds of impurities with different diffusion coefficients are thermally diffused in the fabrication process of the MOS transistor with DDD structure, even though one kind of impurity is implanted in self-alignment with the gate electrode in advance, the impurity ions in the subsequent implantation diffuse into the gate electrode side (channel side) such that the impurity layer overlaps with the gate electrode. As a result, the distance between the source and the drain, which is the effective gate length, becomes small. Moreover, since the impurity ions diffuse isotropically, they also diffuse toward the lower side of the substrate, increasing the junction depth (Xj) of the source-drain diffused layer. As a result, the short channel effect tends to occur easily in this case.
Moreover, if in the MOS transistor with LDD structure the impurity concentration of the impurity layer (LDD layer) directly below the sidewall insulating film is high, the short channel effect tends to occur by the same reasons as in the MOS transistor with DDD structure. On the other hand, if the impurity concentration in the LDD layer is low, the electric field strength in the vicinity of the drain becomes high, which makes easier generation of the hot carriers and increases the parasitic resistance. These factors work as the causes for lowering the driving current.
Furthermore, since the parameters determining the maximum electric field strength of the LDD structure depend strongly on the impurity concentration in the LDD region and the width of the sidewall insulating film, there is a tendency of designing the width of the sidewall insulating film to be small in order to enhance the current drive capability of the MOS transistor. Needless to say, making the width of the sidewall insulating film small, leads to the reduction in the size of the LDD region and the reduction in the relaxation effect of the electric field strength.
Moreover, in the case of an n-channel MOS transistor, the impurity to be implanted into the LDD region is normally phosphorus. However, if ions of an impurity are implanted to such an extent as to reduce the parasitic resistance, impurity diffusion will take place during the heat treatment in the fabrication process, resulting in the generation of the short channel effect as described above. In order to prevent the diffusion of the impurity in the lateral direction, for example, the impurity to be implanted into the LDD region may be switched from phosphorus to arsenic which has a relatively small diffusion coefficient. However, arsenic has a steeper concentration gradient than phosphorus, and changes the carrier distribution markedly, so that it gives rise to a separate problem of increasing the electric field strength.
On the other hand, various kinds of fabrication methods of the MOS transistor aimed at the reduction of the short channel effect and the suppression of generation of hot carriers have been proposed (for example, Publication of Unexamined Patent Applications, No. Sho 63-73669). FIG. 14(a) to FIG. 15(c) are sectional views for describing the fabrication method of MOS transistor arranged in the order of its fabrication processes disclosed in Publication of Unexamined Patent Applications, No. Sho 63-73669. In the method of fabrication described in the Publication, as shown in FIG. 14(a), first, an element isolation film 92 is formed on a p-type semiconductor substrate 91 by selective oxidation. Next, a gate oxide film 93 is formed by subjecting the sample to a thermal oxidation.
Then, ions of phosphorus 95 being a first n-type impurity are implanted to form a first n-type impurity layer 95a. In this case, the implantation energy of ions is about 70 keV, and its dose is 1xc3x971011 to 1xc3x971012 cmxe2x88x922.
Next, as shown in FIG. 14(b), a gate electrode 94 is formed on the gate insulating film 93.
Then, as shown in FIG. 14(c), a first resist mask 102 covering the planned region for drain formation and having an opening in the planned region for source formation is formed. After that, ions of boron 101 being a first p-type impurity are implanted into the principal surface of the semiconductor substrate, to form a first p-type impurity layer 101a. In this case, the energy of ion implantation is about 25 keV, and its dose is 1xc3x971012 to 1xc3x971014 cmxe2x88x922.
Further, as shown in FIG. 15(a), after removal of the first resist mask 102, a second resist mask 103 covering the planned region for source formation and having an opening in the planned region for drain formation is formed. After that, phosphorus 106 being a second n-type impurity is implanted into the principal surface of the semiconductor substrate to form a second n-type impurity layer 106a. In this case, the ion implantation energy is about 70 keV, and its dose is about 5xc3x971013 cmxe2x88x922.
Next, as shown in FIG. 15(b), ions of arsenic being a third n-type impurity are implanted to form a third n-type impurity layer 98a in self-alignment with a gate electrode 104. In this case, the ion implantation energy is about 70 keV, and its dose is about 4xc3x971015 cmxe2x88x922.
Then, after forming a layer insulating film 100 on the entire surface and forming a contact hole or the like, a structure as shown in FIG. 15(c) is obtained by subjecting the sample to a heat treatment.
In the MOS transistor fabricated by this method the drain has a double structure consisting of two kinds of n-type impurities so that the generation of hot carriers is suppressed. In addition, the source has a double structure having both of an n-type and a p-type impurities, and a depletion region is formed below the gate electrode which forms a local enhancement region. As a result of combination of these the short channel effect is effectively suppressed.
However, the MOS transistor fabricated according to this method has a limitation for the application to devices having a gate length of submicron order, because it has a double drain structure. Moreover, since the formation of a transistor with an asymmetric source-drain structure requires a large number of lithography processes for the formation of an n-channel MOSFET, it leads to a problem that a huge amount of time and cost is needed.
In addition to the fabrication method described in the above, there is proposed a method of fabrication of a semiconductor device which reduces the resistance between a conductive layer filled in a contact hole and a diffused layer (Publication of Unexamined Patent Applications, No. Hei 1-94667). In the fabrication method disclosed in this Publication, phosphorus ions are implanted following the implantation of arsenic ions into a polycrystalline silicon film. The implantation energy of arsenic ions is 20 to 100 keV and its dose is 1xc3x971015 to 1xc3x971017 cmxe2x88x922, and the ion implantation energy of phosphorus is 40 to 150 keV and its dose is 1xc3x971013 to 1xc3x971015 cmxe2x88x922. With this arrangement, the range of phosphorus implantation becomes closer to the thickness of the polycrystalline silicon film than to the range of arsenic implantation, and a peak of impurity distribution appears in the vicinity of interface with a silicon substrate.
In a semiconductor device fabricated in this manner, it is possible to take both of the advantage of phosphorus ion implantation and the advantage of arsenic ion implantation, so that the junction depth (Xj) of the source-drain diffused layer can be made small and the resistance to hot carriers can be enhanced.
Moreover, fabrication method of semiconductor device which obviates the thermal diffusion process has been proposed (Publication of Unexamined Patent Applications, No. Hei 5-36719). In the fabrication method of the semiconductor device disclosed in this Publication, first, ions of an n-type impurity such as phosphorus are implanted at a dose of about 1xc3x971013 cmxe2x88x922 in the direction tilted by 45xc2x0 to the surface of a semiconductor substrate. Next, ions of an n-type impurity such as phosphorus or arsenic are implanted at a dose of about 1xc3x971014 cmxe2x88x922 in the direction tilted by 45xc2x0 to the surface of the substrate. Then, ions of an n-type impurity such as arsenic are implanted at a dose of about 1xc3x971015 cmxe2x88x922 in the direction perpendicular to the substrate surface.
According to such a method, ions of n-type impurities are implanted for two times in the direction tilted by 45xc2x0 to the semiconductor substrate, so that the thermal diffusion process for impurity diffusion becomes unnecessary, and it is possible to form a MOS transistor with LDD structure in which a low concentration impurity layer is aligned at high precision with the gate electrode.
Still further, in a semiconductor device having a floating gate which is used for an EEPROM or the like, a semiconductor device with drain diffused layer of double layer structure has been proposed (Publication of Unexamined Patent Applications, No. Hei 6-188429). In the semiconductor device disclosed in this Publication, a floating gate is formed on a gate oxide film, and a control gate is formed on the floating gate via an insulating film. Further, a drain diffused layer is composed of a heavily doped region and a lightly doped region surrounding the heavily doped region having an impurity concentration lower than that of the heavily doped region.
With such a structure it is possible to make the drain diffused layer to be resistant to high voltage, and as a result to improve the number of times of rewriting when the structure is applied to a storage device.
However, with these techniques it is difficult to make the suppression of the hot carrier generation and the suppression of the short channel effect compatible.
Now, a high speed operation is required for semiconductor integrated circuits of recent years, and more particularly a high current drive capability is demanded of the MOS transistors. Although the reduction in the width of the sidewall insulating film is desired in order to improve the current drive capability, it results in an increase in the maximum electric field strength which promotes the generation of the hot carriers, as mentioned above. On the other hand, if the impurity amount of phosphorus, to be ion implanted into the LDD region for the purpose of relaxing the maximum current drive capability, is increased, the overlap of the LDD region with the gate electrode is increased and the short channel effect is promoted. In this way, there is a problem in that the reliability of the MOS transistor is deteriorated if one tries to enhance the current drive capability.
Moreover, as the width of the sidewall insulating film is decreased in the MOS transistor with LDD structure, the sidewall insulating film behaves as if it is a gate oxide film, and the generated hot carriers are implanted not only into the gate oxide film but also into the sidewall insulating film, which gives rise to a problem that the characteristics of the MOS transistor are deteriorated substantially.
It is therefore an object of the present invention to provide an improved semiconductor device, which is capable of suppressing the short channel effect without deteriorating the current drive capability of the MOS transistor, and to reduce the generation of the hot carriers.
The semiconductor device according to the present invention includes a semiconductor substrate having a channel region, a gate insulating film formed on said channel region, a gate electrode formed on a said gate insulating film, said gate electrode having side surfaces, side walls formed on an associated one of said side surfaces of said gate electrode, source and drain regions formed in said semiconductor substrate, and LDD regions formed in said semiconductor substrate, each of which is covered with an associated one of said side walls, each of said LDD regions including at least two kinds of impurities.